Microprocessor & Interfaces

Microprocessor & Interfaces (4AID3-04)

Objective:

To provide students with in-depth understanding of 8085 microprocessor architecture, programming, and interfacing with peripheral devices for real-world applications.

Scope:

• Internal architecture and pin description of 8085
• Assembly language programming, instruction set, addressing modes
• Interrupt handling, subroutines, macros, stack operations
• Interfacing: 8255 PPI, 8254 Timer, 8279 Keyboard/Display
• Serial/Parallel communication: 8251 USART, RS232C, RS422A, IEEE 488
• Applications: 7-segment display, LCD, matrix keyboard

Course Outcomes (COs):

Syllabus Overview:

Microprocessor

A silicon chip (IC) that contains the CPU — performs arithmetic, logic, and control operations. Requires external memory (RAM/ROM) and I/O chips.

Examples: Intel 8085, 8086, Pentium; AMD Ryzen

Microcontroller

A single chip containing CPU + RAM + ROM + I/O ports + timers + serial comm — everything on one chip. Designed for dedicated/embedded applications.

Examples: Intel 8051, PIC16F877, Arduino (ATmega328), STM32

Comparison:

Generations of Microprocessors:

8085 Key Facts:

• 8-bit data bus, 16-bit address bus
• Clock: 3 MHz, 40-pin DIP
• 74 instruction types, ~246 opcodes
• Manufactured by Intel (1977)

8085 Microprocessor Internal Architecture

1. Accumulator (A) — 8-bit

Primary working register. All arithmetic/logic operations use accumulator as one operand and store result here.

2. General Purpose Registers — 8-bit each

B, C, D, E, H, L — can be used individually or as 16-bit pairs (BC, DE, HL).

• HL pair: Most versatile — acts as memory pointer (M = memory at [HL])

3. Flags Register — 8-bit

5 condition flags after ALU operations:

Bit: D7  D6  D5  D4  D3  D2  D1  D0
      S   Z   -  AC   -   P   -  CY

• S (Sign): 1 if result negative (MSB=1)
• Z (Zero): 1 if result is zero
• AC (Auxiliary Carry): Carry from D3 to D4 (used by DAA)
• P (Parity): 1 if result has even number of 1s
• CY (Carry): 1 if carry generated

4. ALU (Arithmetic Logic Unit)

Performs: Add, Subtract, AND, OR, XOR, Compare, Rotate, Complement

Inputs: Accumulator + Temp register → Output to Accumulator

5. Temporary Register — 8-bit

Holds second operand for ALU operations. Not user-accessible.

6. Program Counter (PC) — 16-bit

Always points to address of NEXT instruction to be fetched.

Automatic increment after each fetch.

7. Stack Pointer (SP) — 16-bit

Points to top of stack in RAM. Decrements on PUSH, increments on POP.

8. Instruction Register & Decoder

Stores fetched opcode; decoder converts it to control signals.

9. Timing & Control Unit

Generates ALE, RD̄, WR̄, IO/M̄, S0, S1 control signals.

10. Interrupt Control

Handles TRAP, RST7.5, RST6.5, RST5.5, INTR interrupts.

11. Serial I/O Control

SID (Serial Input Data), SOD (Serial Output Data) — 1-bit serial I/O.

8085 Bus Organization

A bus is a group of wires used to transfer data/address/control signals.

1. Address Bus (A15–A8) — 8 lines, Unidirectional

• 8-bit HIGH address (A15–A8) — always address only
• Unidirectional: 8085 → Memory/IO (output only)
• Together with lower 8 bits → 16-bit address → 2¹⁶ = 64KB addressable space

2. Multiplexed Address/Data Bus (AD7–AD0) — 8 lines, Bidirectional

• MULTIPLEXED: Same 8 lines carry:
• Address (low byte A7–A0) during T1 state (ALE=HIGH)
• Data (D7–D0) during T2/T3 states (ALE=LOW)
• Bidirectional: read (memory→CPU) and write (CPU→memory)

Demultiplexing using ALE:

AD0-AD7  →→  74LS373 Latch  →→  A0-A7 (stable address)
                  ↑ LE
                 ALE signal

When ALE=HIGH: Latch captures address A0–A7

When ALE=LOW: Data flows through bus; latch holds address stable

3. Control Bus — Multiple signals

Memory Space: 16-bit address → 0000H to FFFFH → 64KB total

I/O Space: 8-bit address (lower 8 of address bus) → 00H to FFH → 256 I/O ports

8085 Pin Description (40-pin DIP)

Address Bus Pins (A15–A8): Pins 21–28

• 8-bit unidirectional address bus (high byte)
• Combined with AD0–AD7 to form 16-bit address

Multiplexed Address/Data Pins (AD7–AD0): Pins 12–19

• 8-bit bidirectional multiplexed bus
• During T1: A7–A0 (lower address); During T2+: D7–D0 (data)
• Demultiplexed using 74LS373 latch triggered by ALE

Control & Status Pins:

Interrupt Pins:

Serial I/O Pins:

• Pin 4: SOD — Serial Output Data (1-bit output)
• Pin 5: SID — Serial Input Data (1-bit input)
• Controlled by SIM/RIM instructions

Power & Clock:

• Pin 20: VCC (+5V supply)
• Pin 21: VSS (Ground)
• Pin 1: X1, Pin 2: X2 (Crystal/RC for clock input)
• Pin 22: CLK OUT (Clock output, ½ crystal frequency)
• Pin 3: RESET OUT (Reset propagation to peripherals)
• Pin 23: RESET IN (Active LOW resets CPU, PC←0000H)

Why Multiplexing?

Intel wanted a 40-pin package for 8085 but needed:

• 16-bit address bus (A15–A0) = 16 pins
• 8-bit data bus (D7–D0) = 8 pins

Total = 24 dedicated pins — too many for 40-pin DIP after power/control.

Solution: Multiplex lower 8 address bits with 8 data bits on same 8 pins (AD7–AD0).

Machine Cycle Timing:

T1 state: ALE = HIGH
  AD7–AD0 carry LOW ADDRESS (A7–A0)
  A15–A8 carry HIGH ADDRESS

T2 state: ALE = LOW
  AD7–AD0 carry DATA (D7–D0)
  74LS373 latch holds A7–A0 stable

T3 state: Data read/written

Demultiplexing Circuit:

8085 AD0–AD7 ──────────────────── D0–D7 (to data bus)
              └───► 74LS373 ────► A0–A7 (stable address)
                       ↑
                      ALE (Latch Enable)

74LS373 (Octal Transparent Latch):

• When LE (Latch Enable) = HIGH: Output follows input (transparent)
• When LE = LOW: Output latches/holds last value
• ALE goes HIGH during T1 → latch captures A0–A7
• ALE goes LOW → latch holds address; bus free for data

Benefits of Multiplexing:

• Reduces pin count from 40+ to exactly 40 pins
• Cost reduction, smaller package

Drawbacks:

• Requires external latch (74LS373 or 8212)
• Adds small propagation delay
• More complex circuit design

System Bus after Demultiplexing:

Full 16-bit Address Bus: A15–A8 (direct) + A7–A0 (from latch)
Full 8-bit Data Bus: D7–D0 (from AD7–AD0 in T2/T3)

Static RAM (SRAM)

• Stores data using flip-flop circuits (6 transistors per cell)
• Retains data as long as power is ON — no refresh needed
• Fast access time (5–25 ns)
• Expensive, low density
• Low power consumption in standby
• Use: Cache memory (L1, L2, L3), registers

Dynamic RAM (DRAM)

• Stores data as charge in capacitor (1 transistor + 1 capacitor)
• Needs periodic REFRESH (every 2ms) — charge leaks
• Slower than SRAM, but cheaper and higher density
• Refresh circuitry adds complexity
• Use: Main system memory

SRAM vs DRAM:

Types of ROM:

8085 Memory Map:

• 16-bit address bus → 2¹⁶ = 65,536 bytes = 64KB total
• Address range: 0000H to FFFFH

Typical 8085 system memory map:

0000H – 07FFH  ROM (2KB) — Program storage
0800H – 0FFFH  ROM (2KB) — Extended program
2000H – 27FFH  RAM (2KB) — Data storage
2800H – 2FFFH  RAM (2KB) — Stack/data

Actual map depends on chip select (CS̄) decoder design.

Think of registers as small, super-fast scratchpads inside the CPU where it temporarily stores data while working.

The Main Scratchpads (Registers):

• Accumulator (A): The 'boss' register. Every math or logic calculation happens here, and the final answer is always saved back here. It holds 8 bits (1 byte) of data.
• General Purpose Registers (B, C, D, E, H, L): Six standard 8-bit scratchpads. You can use them individually, or pair them up (BC, DE, HL) to hold larger 16-bit numbers (like memory addresses).
• HL Pair: The most special pair. It acts like a pointing finger — whatever 16-bit address is inside the HL pair, the CPU looks at that specific memory location (called 'M').
• Program Counter (PC - 16 bit): The 'bookmark'. It always remembers the address of the very next instruction the CPU needs to read.
• Stack Pointer (SP - 16 bit): Another pointing finger, but this one always points to the top of the 'Stack' (a temporary pile of data in RAM).

The Flag Register (The Status Board):

This is an 8-bit register where only 5 bits are used. It acts like a set of light bulbs that turn ON (1) or OFF (0) after a math calculation to tell you about the result:

• 1. Sign (S): Turns ON if the answer is a negative number.
• 2. Zero (Z): Turns ON if the answer is exactly zero.
• 3. Carry (CY): Turns ON if an addition was too big and 'carried over' an extra bit (like carrying a 1 in addition).
• 4. Parity (P): Turns ON if the answer has an even number of 1s in its binary form.
• 5. Auxiliary Carry (AC): A special carry used internally when doing decimal (BCD) math.

The 8085 microprocessor understands 74 different basic commands, called its Instruction Set. We group them into 5 simple categories based on what they do:

1. Data Transfer (The Movers):

These commands just copy data from one place to another. They are very safe and never change the flag lightbulbs.

• Example: MOV A, B (Copy what is in register B into the Accumulator A)
• Example: MVI A, 05H (Directly put the number 05 into A)

2. Arithmetic (The Calculators):

These do basic math: add, subtract, increase by 1 (increment), or decrease by 1 (decrement). Because they do math, they change the flags to show if the result was zero, negative, etc.

• Example: ADD B (Add the value in B to A, save result in A)
• Example: INR C (Increase the value in C by 1)

3. Logical (The Decision Makers):

These perform binary logic operations (AND, OR, NOT, XOR) and comparisons. They also change the flags.

• Example: CMA (Complement A — flip all 0s to 1s, and 1s to 0s)
• Example: CMP B (Compare the value in B with A to see which is bigger)

4. Branching (The Jumpers):

Normally, the CPU reads instructions one by one in order. Branch instructions tell the CPU to jump to a completely different part of the program, either always (unconditional) or only if a certain flag is ON (conditional).

• Example: JMP 2000H (Stop what you are doing and jump directly to memory address 2000H)
• Example: JZ 2000H (Jump to 2000H only if the Zero flag is ON)

5. Machine Control (The Hardware Controllers):

These commands control the CPU hardware itself, like stopping the processor or controlling interrupts.

• Example: HLT (Halt — stop processing completely)
• Example: NOP (No Operation — do absolutely nothing for one cycle, used to waste a tiny bit of time)

Every instruction needs data to work on (called an operand). An Addressing Mode is simply the method the CPU uses to find that data. The 8085 has 5 ways to find its data:

1. Immediate Addressing (Data is handed right to it)

The data is provided directly inside the instruction itself. The CPU doesn't have to go looking for it.

• Example: MVI A, 45H (Put the number 45H immediately into A)

2. Register Addressing (Data is in a scratchpad)

The data is sitting in one of the internal registers (A, B, C, etc.). This is the fastest method because the CPU doesn't have to look outside into memory.

• Example: MOV A, B (Find the data in register B, copy it to A)

3. Direct Addressing (Data is at a specific house address)

The instruction gives the exact, full 16-bit memory address where the data lives. The CPU has to travel out to that exact RAM address to get it.

• Example: LDA 2050H (Go to memory address 2050H, take the data there, and put it in A)

4. Register Indirect Addressing (The address is written in a scratchpad)

The instruction doesn't give the address directly. Instead, it tells the CPU to look inside a register pair (usually HL) to find the address, and then go to that address in memory to get the data.

• Example: MOV A, M (Look at the HL pair to find an address. Go to that address in memory, grab the data, and put it in A)

5. Implicit / Implied Addressing (Data location is obvious)

The instruction is so simple that the CPU already knows exactly what data to work on without being told. The data is "implied".

• Example: CMA (Complement Accumulator. The CPU knows it MUST flip the bits inside the Accumulator A. No other location is possible.)

Assembly Language is a low-level language that uses short English-like words (called mnemonics) instead of raw binary 1s and 0s to tell the CPU what to do.

Instruction Format (Size):

Instructions take up different amounts of space in memory depending on how much info they need:

• 1-Byte Instruction: Just the command itself. (e.g., MOV A, B).
• 2-Byte Instruction: The command + 8 bits of data. (e.g., MVI A, 05H).
• 3-Byte Instruction: The command + a full 16-bit address. (e.g., LDA 2050H).

Note: 16-bit addresses are stored "Little Endian", meaning the lower half of the address is stored first, then the upper half.

Basic Program Example: Add Two Numbers

Imagine we want to take a number from memory address 2050H, add it to a number in 2051H, and save the answer in 2052H.

Here is how we write it:

ORG 2000H     ; Tell the assembler to start the program at address 2000H
LDA 2050H     ; Step 1: Go to 2050H, get the 1st number, put it in A
MOV B, A      ; Step 2: Copy that 1st number into B to keep it safe
LDA 2051H     ; Step 3: Go to 2051H, get the 2nd number, put it in A
ADD B         ; Step 4: Add the 1st number (in B) to the 2nd number (in A)
STA 2052H     ; Step 5: Take the final answer from A and save it at 2052H
HLT           ; Step 6: Halt (Stop the program)

Assembler Directives:

Words like ORG (Origin) or END are not instructions for the microprocessor. They are notes for the Assembler software (the translator program) to tell it how to organize the code.

To understand how fast a program runs, we have to look at how the CPU breaks down time. Imagine the CPU's internal clock ticking constantly.

1. T-State (The Smallest Tick)

A T-State is simply one single tick of the CPU's internal clock. If the processor runs at a frequency of 3 MHz (3 million ticks per second), one T-State takes exactly 333 nanoseconds. It is the smallest possible unit of time.

2. Machine Cycle (One Fetch or Memory Trip)

The CPU cannot read memory and understand an instruction in just one tick. A Machine Cycle is the time it takes to complete ONE specific task over the bus system (like grabbing a byte from memory, or writing a byte to memory).

• A Machine Cycle is made up of multiple T-States grouped together (usually 3 to 6 ticks).
• Example: The first thing the CPU does is an Opcode Fetch cycle (fetching the command itself). This usually takes 4 T-States.
• Example: A Memory Read cycle (fetching the data) takes 3 T-States.

3. Instruction Cycle (The Full Job)

An Instruction Cycle is the total time needed to completely fetch, decode, and execute ONE full instruction.

• An Instruction Cycle is made up of one or more Machine Cycles.

Putting it all together (Example):

Let's look at the instruction MVI A, 05H (Put data 05 into A).

• 1. First, the CPU needs to read the command 'MVI A' from memory. This is an Opcode Fetch machine cycle (takes 4 T-States).
• 2. Next, the CPU needs to read the actual data '05H' from the next memory slot. This is a Memory Read machine cycle (takes 3 T-States).
• 3. Total Time: 4 + 3 = 7 T-States.

If our clock is 3 MHz, this entire instruction takes 7 × 333 nanoseconds = 2.33 microseconds to execute.

Because microprocessors operate incredibly fast (in microseconds), we often need to force them to slow down to interact with humans or slower hardware (like blinking an LED so you can see it). We do this using Software Time Delays.

How a Time Delay Works:

A software delay is basically a 'do-nothing loop'. You tell the CPU to load a large number into a register, and then count down to zero. Because each subtraction (DCR) and jump (JNZ) takes a specific number of T-States (clock ticks), we can calculate exactly how long the loop will take.

Example Delay Loop:

DELAY:
  MVI B, 255     ; Load the maximum 8-bit count (255)
LOOP:
  DCR B          ; Decrease B by 1 (Takes 4 T-states)
  JNZ LOOP       ; If B is not zero, jump back (Takes 10 T-states)
  RET            ; Return when done

Math: One loop takes 14 T-States. 255 loops × 14 = 3570 T-States. At 3 MHz, this wastes about 1.19 milliseconds.

Nested Delays for Longer Times:

If you need a 1-second delay, an 8-bit counter (max 255) isn't enough. We use a Nested Loop (a loop inside a loop). The inner loop counts down to 0, then the outer loop decreases by 1, and the inner loop starts counting down all over again.

Software Counters:

A counter works similarly but counts up. You start at zero, add 1, do something (like save it to memory or show it on a display), and keep repeating until you reach a target number.

An Interrupt is an emergency signal from an external device (like a keyboard or sensor) asking the CPU to stop what it's currently doing and handle a more urgent task.

Imagine you are reading a book (the main program) and the doorbell rings (the interrupt). You put a bookmark in the page (save the Program Counter), go answer the door (the Interrupt Service Routine), and when finished, you come back to exactly where you left off.

The 5 Interrupt Pins (from Highest to Lowest Priority):

• 1. TRAP (Highest Priority): This is Non-Maskable. You cannot turn it off. It is the ultimate emergency signal, usually used for critical hardware failures like power loss.
• 2. RST 7.5: Second highest priority.
• 3. RST 6.5: Third highest.
• 4. RST 5.5: Fourth highest.
• 5. INTR (Lowest Priority): The standard interrupt request pin.

Maskable vs. Non-Maskable:

• Maskable: Think of these as a phone ringtone that you can put on silent (masked) using software commands. If masked, the CPU will ignore them. RST 7.5, 6.5, 5.5, and INTR are all maskable.
• Non-Maskable: The TRAP interrupt is like a fire alarm. You cannot mute it. The CPU must respond to it immediately, no matter what it is doing.

Control Commands:

• EI (Enable Interrupts): Turns the "ringer" ON for all maskable interrupts.
• DI (Disable Interrupts): Turns the "ringer" OFF (masks them).
• SIM (Set Interrupt Mask): A special command to individually turn on/off the specific RST 7.5, 6.5, and 5.5 interrupts.

The 8085 CPU only has a few physical pins for interrupts. But what if you have a complex system with a keyboard, mouse, printer, timer, and disk drive all trying to get the CPU's attention at the same time?

To solve this, we use a helper chip called the 8259 Programmable Interrupt Controller (PIC). It acts like a receptionist for the CPU.

Why we need it:

It expands the CPU's single INTR pin into 8 separate interrupt input lines (labeled IR0 to IR7). You can even chain multiple 8259 chips together to handle up to 64 devices!

How it works (The Receptionist Analogy):

• 1. Requests Arrive: Several external devices trigger the IR lines (IR0, IR2, IR5) at the same time. The 8259 records these requests in its Interrupt Request Register (IRR) (the waiting room).
• 2. Priority Resolution: The 8259's internal Priority Resolver decides which device is the most important. By default, IR0 is the highest priority and IR7 is the lowest.
• 3. Alerting the Boss: The 8259 sends a single INT signal to the 8085 CPU, effectively saying, "Boss, someone important is here."
• 4. Acknowledgement: The 8085 finishes its current instruction and sends an INTA (Acknowledge) signal back, saying "Okay, send them in."
• 5. Passing the Vector: The 8259 then places a specific address (vector) on the data bus. The CPU jumps to this exact address to find the code needed to handle that specific device.
• 6. In-Service: While the CPU handles the request, the 8259 marks that interrupt in its In-Service Register (ISR) so it knows not to interrupt the CPU with a lower-priority task until the current one is finished.

The Stack (LIFO):

The Stack is a designated area in the RAM used for temporary storage. It works like a stack of cafeteria plates — the last plate you put on top is the first one you take off. This is called LIFO (Last-In, First-Out). The Stack Pointer (SP) register always keeps track of the top plate.

PUSH and POP:

• PUSH B: Takes the 16-bit data inside the BC register pair and pushes it onto the top of the stack. The Stack Pointer moves down by 2 memory addresses to make room.
• POP B: Grabs the top 16 bits of data off the stack and puts it back into the BC pair. The Stack Pointer moves up by 2.

Subroutines (Reusable Code):

If you need to calculate a square root 10 different times in your program, writing the math code 10 times wastes memory. Instead, you write the math code once, put it in a separate block called a Subroutine, and use the CALL instruction whenever you need it.

• CALL address: The CPU pushes its current place (the Program Counter) onto the Stack as a bookmark, then jumps to the subroutine.
• RET (Return): Placed at the end of the subroutine. It pops the bookmark off the Stack and puts it back in the PC, so the CPU jumps back to exactly where it left off.

Macro vs. Subroutine:

• Subroutine: The code exists in only one place in memory. The program jumps to it using CALL. It saves memory space but runs slightly slower due to jumping back and forth.
• Macro: A shortcut used by the assembler software. When you use a Macro name, the assembler literally copies and pastes the full block of code directly into your program at that spot. It runs faster (no jumping) but takes up more memory space if used multiple times.

Memory Interfacing is the physical wiring required to connect external memory chips (like RAM or ROM) to the microprocessor so they can communicate successfully.

The Problem: Too Many Chips, One Bus

The 8085 has a single 8-bit Data Bus. If you connect multiple memory chips to this one bus, they can't all talk at the same time, or the signals will crash into each other. The CPU must only talk to one chip at a time.

The Solution: Chip Select (CS)

Every memory chip has a special pin called Chip Select (CS) or Chip Enable (CE). When this pin gets a LOW signal (0V), the chip turns ON and connects to the data bus. When the pin is HIGH (5V), the chip goes to sleep and disconnects from the bus.

Address Decoding (Acting as the Traffic Cop):

How do we ensure only one CS pin goes LOW at a time? We use Address Decoding.

The 8085 has 16 address lines (A0 to A15), which can address 64KB of memory. If a small 2KB memory chip only needs 11 lines (A0-A10) to find its internal data, what do we do with the leftover top lines (A11-A15)?

We feed those top lines into a Decoder circuit (like the 74LS138 chip or logic gates).

How it works:

• 1. The CPU outputs a 16-bit address (e.g., trying to read address 2000H).
• 2. The lower lines go directly into the memory chip to find the exact byte.
• 3. The upper lines go into the Decoder.
• 4. The Decoder checks the combination of the upper lines. If it matches the specific range assigned to a RAM chip, it outputs a LOW signal directly to that specific RAM chip's CS pin.
• 5. The correct chip wakes up, and all other chips stay asleep. This guarantees no data collisions!

The microprocessor is the brain, but it needs a way to connect to external devices like LEDs, switches, and printers. The 8255 Programmable Peripheral Interface (PPI) is a general-purpose connecting chip that bridges the gap between the CPU and the outside world.

The Ports (The Doors):

The 8255 provides 24 physical connection pins grouped into three 8-bit 'doors' or Ports:

• Port A (8-bit): Can be set as input or output.
• Port B (8-bit): Can be set as input or output.
• Port C (8-bit): Special port. It can act as a standard 8-bit port, or it can be split into two 4-bit halves (Upper and Lower). Often, its pins are used as control signals to help Ports A and B communicate smoothly.

The 3 Operating Modes:

You program the 8255's Control Register to tell it how to behave.

• 1. Mode 0 (Simple I/O): This is the most basic mode. Data just flows straight in or straight out. It assumes the external device is always ready. Example: Lighting up simple LEDs or reading simple switches.
• 2. Mode 1 (Strobed I/O with Handshaking): The CPU operates much faster than a printer. If it sends data too fast, the printer will drop characters. In Mode 1, Port A and Port B use pins from Port C to "shake hands" with the device. The 8255 sends a byte, then waits for a "Strobe" signal from the printer saying, "Okay, I got it, send the next one."
• 3. Mode 2 (Bidirectional I/O): Used only by Port A. Data can flow in BOTH directions on the same pins. It heavily relies on Port C pins to manage traffic and ensure data doesn't crash.

BSR Mode (Bit Set/Reset):

This is a special secondary feature where you can individually flip a single pin on Port C ON or OFF without affecting the other pins.

In Unit 4, we learned how to make the CPU wait using a software delay loop (counting down a register). However, when the CPU is counting down, it is fully occupied and cannot do any other work.

The 8254 Programmable Interval Timer solves this. It is a separate hardware chip that handles timing and counting independently, completely freeing up the CPU to do real work.

Internal Architecture:

The 8254 contains three independent 16-bit counters (Counter 0, Counter 1, and Counter 2).

Each counter has three connections:

• CLK (Clock In): The heartbeat it counts down from.
• GATE (Control): A switch to start, stop, or pause the counter.
• OUT (Result): The pin where the final timing signal or pulse comes out.

The 6 Operating Modes:

You can program each counter to act differently depending on what you need:

• 1. Mode 0 (Interrupt on Terminal Count): You load a number. It counts down to zero, and then the OUT pin goes HIGH. Use: Triggering an alarm after exactly 5 seconds.
• 2. Mode 1 (Programmable One-Shot): The counter waits for a trigger signal on the GATE pin, then outputs a single, precise pulse of a specific length. Use: Hardware delays.
• 3. Mode 2 (Rate Generator): It acts like a divider. If you input a 1 MHz clock and load it with 1000, it outputs a pulse every 1000 ticks (creating a 1 kHz signal). Use: Generating regular ticks for a digital clock.
• 4. Mode 3 (Square Wave Generator): Similar to Mode 2, but instead of quick pulses, the OUT pin stays HIGH for half the time and LOW for half the time, creating a perfect square wave. Use: Generating audio tones or baud rates.
• 5. Mode 4 & 5 (Software/Hardware Strobe): Used to generate a delayed pulse a specific amount of time after it's triggered.

To read a large keypad (like a calculator) or light up multiple 7-segment displays, the CPU has to constantly run scanning loops. It has to rapidly check every row of the keyboard to see if a key is pressed, and it has to rapidly flash each digit on the display to make them all appear ON at the same time. This takes up a massive amount of the CPU's time.

The 8279 Keyboard/Display Controller is a dedicated chip designed specifically to take over these tedious tasks.

How it works (The Assistant Analogy):

You can think of the 8279 as an assistant. The CPU gives the assistant a block of data and says, "Keep showing this on the display," and the 8279 handles all the rapid flashing automatically. The CPU can then go to sleep or do complex math.

Meanwhile, the 8279 constantly scans the keyboard in the background. When a human presses a key, the 8279 detects it, eliminates the mechanical noise (debouncing), and stores the key code in its internal FIFO (First-In, First-Out) memory buffer. It then taps the CPU on the shoulder (via an Interrupt signal) and says, "Hey, someone pressed a key, the data is ready for you."

Key Features of 8279:

• Display RAM (16x8): It has internal memory to remember what needs to be shown on up to 16 display digits.
• Keyboard FIFO (8x8): An internal waiting room that can store up to 8 key presses if the CPU is too busy to read them immediately.
• Scan Lines: Dedicated pins that handle the rapid sweeping across keyboard rows and display digits.
• Hardware Debouncing: Mechanical buttons act like springs and bounce electrically when pressed. The 8279 waits a few milliseconds to ensure the key press is solid before recording it, preventing phantom double-clicks.

7-Segment Display Interfacing

A single 7-segment display (like on a digital clock) requires 8 pins (7 segments + decimal point). If you have 4 digits, you would normally need 32 pins, which is far too many for a microprocessor to spare.

To solve this, we use Multiplexing (Scanning).

We wire all the 'A' segments together across all four digits, all the 'B' segments together, etc. Then, we connect the power line for each digit separately.

The CPU (or an 8279 chip) turns ON only ONE digit at a time, sends the correct shape to it, waits a tiny fraction of a second, turns it OFF, and moves to the next digit. It does this sweeping motion so fast (over 50 times a second) that our human eyes are fooled by "persistence of vision." To us, it looks like all four digits are solidly ON at the same time.

LCD (Liquid Crystal Display) Interfacing

A standard 16x2 character LCD is much smarter than a simple 7-segment LED. It has its own built-in mini-controller chip.

To interface it via an 8255 port, we connect:

• Data Lines (D0-D7): Where we send the ASCII code of the letter we want to print (e.g., sending 'A').
• RS (Register Select) Pin: We set this to 0 when sending setup commands (like "clear screen"), and we set it to 1 when sending actual text data to print.
• E (Enable) Pin: This is the trigger. After setting up the data on the pins, the CPU pulses the Enable pin HIGH then LOW. This tells the LCD, "Lock in the data now!"

When initialized properly, you can just send ASCII characters to the LCD port, and it handles the complex task of drawing the pixels for the letters.

If you have a keypad with 16 buttons (0-9, A-D, *, #), giving every button its own dedicated wire to the CPU would waste 16 valuable input pins.

Instead, we arrange the buttons in a grid, or a Matrix. A 4x4 matrix has 4 horizontal wires (Rows) crossing over 4 vertical wires (Columns). When you press a button, it acts as a bridge, connecting one specific Row wire to one specific Column wire.

Using this grid, 16 buttons only require 8 wires total (4 rows + 4 columns).

The Keyboard Scanning Algorithm:

To figure out which key is pressed, the CPU (via an 8255 chip) acts like a detective checking rooms in a hotel:

• 1. Drive one Row LOW: The CPU sends a 0V signal down Row 0, and leaves the other rows HIGH (5V).
• 2. Read the Columns: The CPU checks the 4 column wires.
• 3. Check for connection: If all columns read HIGH (1), it means no key in Row 0 is pressed. The CPU moves on, drives Row 1 LOW, and checks again.
• 4. Key Found: If the CPU drives Row 2 LOW, and suddenly detects that Column 3 is also reading LOW (0), it knows a connection has been made! The key pressed is exactly at the intersection of Row 2 and Column 3.
• 5. Debounce: Because metal contacts bounce, the CPU waits about 20 milliseconds, and then checks the row and column one more time. If it's still connected, the CPU confirms the key press and looks up what character that intersection represents.

Parallel vs. Serial Communication:

• Parallel: Sending all 8 bits of a byte simultaneously over 8 separate wires (like an 8-lane highway). It's very fast, but expensive and bulky for long distances.
• Serial: Sending bits one at a time, sequentially down a single wire (like a single-lane road). Slower, but perfect for long distances (like internet cables or USB).

Because the internal 8085 CPU works in parallel (8 bits at once), it needs a translator to communicate serially with the outside world. That translator is the 8251 USART (Universal Synchronous/Asynchronous Receiver/Transmitter).

It takes a parallel byte from the CPU, lines the bits up in a row, and fires them out a single TxD (Transmit) pin. Simultaneously, it can receive a stream of bits on its RxD (Receive) pin, bundle them into an 8-bit byte, and hand it to the CPU.

Serial Standards (How the electrical signals look):

Logic 1 and 0 need specific voltage levels to travel long distances without getting corrupted by interference.

• RS-232C Standard: The classic serial port standard. It uses negative voltage (-3V to -15V) to represent Logic 1, and positive voltage (+3V to +15V) for Logic 0. It uses a single wire relative to a ground wire. It's prone to noise and is only good for short distances (about 15 meters) at lower speeds.
• RS-422A Standard: A modern industrial standard. Instead of measuring against ground, it sends the signal down a twisted pair of wires as a voltage difference (Differential Signaling). If noise hits the cable, it hits both wires equally and cancels out. This allows for massive distances (up to 1200 meters) at very high speeds (10 Mbps).